simulavr  1.1.0
at90canbase.cpp
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1  /*
2  ****************************************************************************
3  *
4  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
5  * Copyright (C) 2001, 2002, 2003 Klaus Rudolph
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  ****************************************************************************
22  */
23 #include "at90canbase.h"
24 
25 #include "irqsystem.h"
26 #include "hwstack.h"
27 #include "hweeprom.h"
28 #include "hwwado.h"
29 #include "hwsreg.h"
30 #include "avrerror.h"
31 #include "avrfactory.h"
32 
36 
38  delete usart1;
39  delete usart0;
40  delete acomp;
41  delete wado;
42  delete spi;
43  delete ad;
44  delete aref;
45  delete admux;
46  delete gpior2_reg;
47  delete gpior1_reg;
48  delete gpior0_reg;
49  delete timer3;
50  delete inputCapture3;
51  delete timerIrq3;
52  delete timer2;
53  delete timerIrq2;
54  delete timer1;
55  delete inputCapture1;
56  delete timerIrq1;
57  delete timer0;
58  delete timerIrq0;
59  delete extirq01;
60  delete eifr_reg;
61  delete eimsk_reg;
62  delete eicrb_reg;
63  delete eicra_reg;
64  delete rampz;
65  delete osccal_reg;
66  delete clkpr_reg;
67  delete stack;
68  delete eeprom;
69  delete irqSystem;
70  delete spmRegister;
71 }
72 
74  unsigned flash_bytes,
75  unsigned ee_bytes ):
76  AvrDevice(224, // I/O space above General Purpose Registers
77  ram_bytes, // RAM size
78  0, // External RAM size
79  flash_bytes), // Flash Size
80  porta(this, "A", true),
81  portb(this, "B", true),
82  portc(this, "C", true, 7),
83  portd(this, "D", true),
84  porte(this, "E", true),
85  portf(this, "F", true),
86  portg(this, "G", true),
87  gtccr_reg(&coreTraceGroup, "GTCCR"),
88  assr_reg(&coreTraceGroup, "ASSR"),
89  prescaler013(this, "01", &gtccr_reg, 0, 7),
90  prescaler2(this, "2", PinAtPort(&portc, 7), &assr_reg, 5, &gtccr_reg, 1, 7),
91  premux0(&prescaler013, PinAtPort(&portd, 7)),
92  premux1(&prescaler013),
93  premux2(&prescaler2),
94  premux3(&prescaler013, PinAtPort(&porte, 6)) {
95  flagELPMInstructions = true;
96  fuses->SetFuseConfiguration(20, 0xff9962);
97  if(flash_bytes > 64U * 1024U) {
98  fuses->SetBootloaderConfig(0xf000, 0x1000, 9, 8);
100  } else {
101  if(flash_bytes > 32U * 1024U) {
102  fuses->SetBootloaderConfig(0x7000, 0x1000, 9, 8);
104  } else {
105  fuses->SetBootloaderConfig(0x3000, 0x1000, 9, 8);
107  }
108  }
109  irqSystem = new HWIrqSystem(this, 4, 37);
110 
111  eeprom = new HWEeprom(this, irqSystem, ee_bytes, 26, HWEeprom::DEVMODE_EXTENDED);
112  stack = new HWStackSram(this, 16);
113  clkpr_reg = new CLKPRRegister(this, &coreTraceGroup);
115 
116  rampz = new AddressExtensionRegister(this, "RAMPZ", 1);
117 
118  eicra_reg = new IOSpecialReg(&coreTraceGroup, "EICRA");
119  eicrb_reg = new IOSpecialReg(&coreTraceGroup, "EICRB");
120  eimsk_reg = new IOSpecialReg(&coreTraceGroup, "EIMSK");
121  eifr_reg = new IOSpecialReg(&coreTraceGroup, "EIFR");
123  extirq01->registerIrq(1, 0, new ExternalIRQSingle(eicra_reg, 0, 2, GetPin("D0")));
124  extirq01->registerIrq(2, 1, new ExternalIRQSingle(eicra_reg, 2, 2, GetPin("D1")));
125  extirq01->registerIrq(3, 2, new ExternalIRQSingle(eicra_reg, 4, 2, GetPin("D2")));
126  extirq01->registerIrq(4, 3, new ExternalIRQSingle(eicra_reg, 6, 2, GetPin("D3")));
127  extirq01->registerIrq(5, 4, new ExternalIRQSingle(eicrb_reg, 0, 2, GetPin("E4")));
128  extirq01->registerIrq(6, 5, new ExternalIRQSingle(eicrb_reg, 2, 2, GetPin("E5")));
129  extirq01->registerIrq(7, 6, new ExternalIRQSingle(eicrb_reg, 4, 2, GetPin("E6")));
130  extirq01->registerIrq(8, 7, new ExternalIRQSingle(eicrb_reg, 6, 2, GetPin("E7")));
131 
132  timerIrq0 = new TimerIRQRegister(this, irqSystem, 0);
133  timerIrq0->registerLine(0, IRQLine("TOV0", 17)); // TIMER0 OVF
134  timerIrq0->registerLine(1, IRQLine("OCF0A", 16)); // TIMER0 COMP
135 
136  timer0 = new HWTimer8_1C(this,
137  &premux0,
138  0,
139  timerIrq0->getLine("TOV0"),
140  timerIrq0->getLine("OCF0A"),
141  PinAtPort(&portb, 7));
142 
143  timerIrq1 = new TimerIRQRegister(this, irqSystem, 1);
144  timerIrq1->registerLine(0, IRQLine("TOV1", 15)); // TIMER1 OVF
145  timerIrq1->registerLine(1, IRQLine("OCF1A", 12)); // TIMER1 COMPA
146  timerIrq1->registerLine(2, IRQLine("OCF1B", 13)); // TIMER1 COMPB
147  timerIrq1->registerLine(3, IRQLine("OCF1C", 14)); // TIMER1 COMPC
148  timerIrq1->registerLine(5, IRQLine("ICF1", 11)); // TIMER1 CAPT
149 
151  timer1 = new HWTimer16_3C(this,
152  &premux1,
153  1,
154  timerIrq1->getLine("TOV1"),
155  timerIrq1->getLine("OCF1A"),
156  PinAtPort(&portb, 1),
157  timerIrq1->getLine("OCF1B"),
158  PinAtPort(&portb, 2),
159  timerIrq1->getLine("OCF1C"),
160  PinAtPort(&portb, 3),
161  timerIrq1->getLine("ICF1"),
162  inputCapture1);
163 
164  timerIrq2 = new TimerIRQRegister(this, irqSystem, 2);
165  timerIrq2->registerLine(0, IRQLine("TOV2", 10)); // TIMER2 OVF
166  timerIrq2->registerLine(1, IRQLine("OCF2A", 9)); // TIMER2 COMP
167 
168  timer2 = new HWTimer8_1C(this,
169  &premux2,
170  2,
171  timerIrq2->getLine("TOV2"),
172  timerIrq2->getLine("OCF2A"),
173  PinAtPort(&portb, 4));
174 
175  timerIrq3 = new TimerIRQRegister(this, irqSystem, 3);
176  timerIrq3->registerLine(0, IRQLine("TOV3", 31)); // TIMER3 OVF
177  timerIrq3->registerLine(1, IRQLine("OCF3A", 28)); // TIMER3 COMPA
178  timerIrq3->registerLine(2, IRQLine("OCF3B", 29)); // TIMER3 COMPB
179  timerIrq3->registerLine(3, IRQLine("OCF3C", 30)); // TIMER3 COMPC
180  timerIrq3->registerLine(5, IRQLine("ICF3", 27)); // TIMER3 CAPT
181 
183  timer3 = new HWTimer16_3C(this,
184  &premux3,
185  3,
186  timerIrq3->getLine("TOV3"),
187  timerIrq3->getLine("OCF3A"),
188  PinAtPort(&portb, 1),
189  timerIrq3->getLine("OCF3B"),
190  PinAtPort(&portb, 2),
191  timerIrq3->getLine("OCF3C"),
192  PinAtPort(&portb, 3),
193  timerIrq3->getLine("ICF3"),
194  inputCapture3);
195 
196  gpior0_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR0");
197  gpior1_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR1");
198  gpior2_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR2");
199 
200  admux = new HWAdmuxM16(this, &portf.GetPin(0), &portf.GetPin(1), &portf.GetPin(2),
201  &portf.GetPin(3), &portf.GetPin(4), &portf.GetPin(5),
202  &portf.GetPin(6), &portf.GetPin(7));
203  aref = new HWARef4(this, HWARef4::REFTYPE_NOBG);
204  ad = new HWAd(this, HWAd::AD_M164, irqSystem, 25, admux, aref);
205 
206  spi = new HWSpi(this,
207  irqSystem,
208  PinAtPort(&portb, 2), // MOSI
209  PinAtPort(&portb, 3), // MISO
210  PinAtPort(&portb, 1), // SCK
211  PinAtPort(&portb, 0), // /SS
212  20, // irqvec
213  true);
214 
215  wado = new HWWado(this);
216 
217  acomp = new HWAcomp(this, irqSystem, PinAtPort(&porte, 2), PinAtPort(&porte, 3), 24, ad, timer1);
218 
219  usart0 = new HWUsart(this,
220  irqSystem,
221  PinAtPort(&porte,1), // TXD
222  PinAtPort(&porte,0), // RXD
223  PinAtPort(&porte,2), // XCK
224  21, // RX complete vector
225  22, // UDRE vector
226  23, // TX complete vector
227  0);
228 
229  usart1 = new HWUsart(this,
230  irqSystem,
231  PinAtPort(&portd,3), // TXD
232  PinAtPort(&portd,2), // RXD
233  PinAtPort(&portd,5), // XCK
234  32, // RX complete vector
235  33, // UDRE vector
236  34, // TX complete vector
237  1);
238 
239 
240  /* 0xfb - 0xff reserved */
241  /* 0xd8 - 0xfa CANBUS TODO */
242  /* 0xcf - 0xd7 reserved */
243  rw[0xce]= & usart1->udr_reg;
244  rw[0xcd]= & usart1->ubrrhi_reg;
245  /* 0xcb reserved */
246  rw[0xca]= & usart1->ucsrc_reg;
247  rw[0xcc]= & usart1->ubrr_reg;
248  rw[0xc9]= & usart1->ucsrb_reg;
249  rw[0xc8]= & usart1->ucsra_reg;
250  /* 0xc7 reserved */
251  rw[0xc6]= & usart0->udr_reg;
252  rw[0xc5]= & usart0->ubrrhi_reg;
253  rw[0xc4]= & usart0->ubrr_reg;
254  /* 0xc3 reserved */
255  rw[0xc2]= & usart0->ucsrc_reg;
256  rw[0xc1]= & usart0->ucsrb_reg;
257  rw[0xc0]= & usart0->ucsra_reg;
258  /* 0xbd - 0xbf reserved */
264  /* 0xb7 reserved */
265  rw[0xb6]= & assr_reg;
266  /* 0xb4 - 0xb5 reserved */
267  rw[0xb3]= & timer2->ocra_reg;
268  rw[0xb2]= & timer2->tcnt_reg;
269  /* 0xb1 reserved */
270  rw[0xb0]= & timer2->tccr_reg;
271  /* 0x9e - 0xaf reserved */
272  rw[0x9d]= & timer3->ocrc_h_reg;
273  rw[0x9c]= & timer3->ocrc_l_reg;
274  rw[0x9b]= & timer3->ocrb_h_reg;
275  rw[0x9a]= & timer3->ocrb_l_reg;
276  rw[0x99]= & timer3->ocra_h_reg;
277  rw[0x98]= & timer3->ocra_l_reg;
278  rw[0x97]= & timer3->icr_h_reg;
279  rw[0x96]= & timer3->icr_l_reg;
280  rw[0x95]= & timer3->tcnt_h_reg;
281  rw[0x94]= & timer3->tcnt_l_reg;
282  /* 0x93 reserved */
283  rw[0x92]= & timer3->tccrc_reg;
284  rw[0x91]= & timer3->tccrb_reg;
285  rw[0x90]= & timer3->tccra_reg;
286  /* 0x8e - 0x8f reserved */
287  rw[0x8d]= & timer1->ocrc_h_reg;
288  rw[0x8c]= & timer1->ocrc_l_reg;
289  rw[0x8b]= & timer1->ocrb_h_reg;
290  rw[0x8a]= & timer1->ocrb_l_reg;
291  rw[0x89]= & timer1->ocra_h_reg;
292  rw[0x88]= & timer1->ocra_l_reg;
293  rw[0x87]= & timer1->icr_h_reg;
294  rw[0x86]= & timer1->icr_l_reg;
295  rw[0x85]= & timer1->tcnt_h_reg;
296  rw[0x84]= & timer1->tcnt_l_reg;
297  // 0x83 reserved
298  rw[0x82]= & timer1->tccrc_reg;
299  rw[0x81]= & timer1->tccrb_reg;
300  rw[0x80]= & timer1->tccra_reg;
301  /* 0x7e-0x7f DIDR TODO */
302  rw[0x7C]= & ad->admux_reg;
303  rw[0x7B]= & ad->adcsrb_reg;
304  rw[0x7A]= & ad->adcsra_reg;
305  rw[0x79]= & ad->adch_reg;
306  rw[0x78]= & ad->adcl_reg;
307  /* 0x76-0x77 reserved */
308  /* 0x74-0x75 External memory control registers TODO */
309  /* 0x72-0x73 reserved */
310  rw[0x70]= & timerIrq2->timsk_reg;
311  rw[0x6F]= & timerIrq1->timsk_reg;
312  rw[0x6E]= & timerIrq0->timsk_reg;
313  /* 0x6b-0x6d Reserved */
314  rw[0x6A]= eicrb_reg;
315  rw[0x69]= eicra_reg;
316  /* 0x67-0x68 Reserved */
317  rw[0x66]= osccal_reg;
318  /* 0x62-0x65 Reserved */
319  rw[0x61]= clkpr_reg;
320  rw[0x60]= & wado->wdtcr_reg;
321  rw[0x5f]= statusRegister;
322  rw[0x5e]= & ((HWStackSram *)stack)->sph_reg;
323  rw[0x5d]= & ((HWStackSram *)stack)->spl_reg;
324  /* 0x5c reserved */
325  rw[0x5b]= & rampz->ext_reg;
326  /* 0x58-0x5A Reserved */
327  rw[0x57]= & spmRegister->spmcr_reg;
328  /* 0x56 Reserved */
329  /* 0x55 MCUCR -- Memory control TODO */
330  /* 0x54 MCUSR -- Memory control TODO */
331  /* 0x53 SMCR -- sleep register TODO */
332  /* 0x52 Reserved */
333  /* 0x51 OCDR */
334  rw[0x50]= & acomp->acsr_reg;
335  /* 0x4f reserved */
336  rw[0x4E]= & spi->spdr_reg;
337  rw[0x4D]= & spi->spsr_reg;
338  rw[0x4C]= & spi->spcr_reg;
339  rw[0x4B]= gpior2_reg;
340  rw[0x4A]= gpior1_reg;
341  /* 0x48 - 0x49 reserved */
342  rw[0x47]= & timer0->ocra_reg;
343  rw[0x46]= & timer0->tcnt_reg;
344  /* 0x45 reserved */
345  rw[0x44]= & timer0->tccr_reg;
346  rw[0x43]= & gtccr_reg;
347  rw[0x42]= & eeprom->eearh_reg;
348  rw[0x41]= & eeprom->eearl_reg;
349  rw[0x40]= & eeprom->eedr_reg;
350  rw[0x3F]= & eeprom->eecr_reg;
351 
352  rw[0x3E]= gpior0_reg;
353  rw[0x3D]= eimsk_reg;
354  rw[0x3C]= eifr_reg;
355 
356  /* 0x39-0x3b Reserved */
357  rw[0x38]= & timerIrq3->tifr_reg;
358  rw[0x37]= & timerIrq2->tifr_reg;
359  rw[0x36]= & timerIrq1->tifr_reg;
360  rw[0x35]= & timerIrq0->tifr_reg;
361 
362  rw[0x34]= & portg.port_reg;
363  rw[0x33]= & portg.ddr_reg;
364  rw[0x32]= & portg.pin_reg;
365 
366  rw[0x31]= & portf.port_reg;
367  rw[0x30]= & portf.ddr_reg;
368  rw[0x2F]= & portf.pin_reg;
369 
370  rw[0x2E]= & porte.port_reg;
371  rw[0x2D]= & porte.ddr_reg;
372  rw[0x2C]= & porte.pin_reg;
373 
374  rw[0x2B]= & portd.port_reg;
375  rw[0x2A]= & portd.ddr_reg;
376  rw[0x29]= & portd.pin_reg;
377 
378  rw[0x28]= & portc.port_reg;
379  rw[0x27]= & portc.ddr_reg;
380  rw[0x26]= & portc.pin_reg;
381 
382  rw[0x25]= & portb.port_reg;
383  rw[0x24]= & portb.ddr_reg;
384  rw[0x23]= & portb.pin_reg;
385 
386  rw[0x22]= & porta.port_reg;
387  rw[0x21]= & porta.ddr_reg;
388  rw[0x20]= & porta.pin_reg;
389 
390  Reset();
391 }
392 
ADC reference is selected on 3 or 4 different sources: Vcc, aref pin, bandgap or 2.56V reference.
Definition: hwad.h:60
HWUsart * usart1
usart 1 unit
Definition: at90canbase.h:77
GPIORegister * gpior0_reg
Definition: at90canbase.h:90
Basic AVR device, contains the core functionality.
Definition: avrdevice.h:66
0:aref, 1:vcc, 2:-, 3:2.56V
Definition: hwad.h:67
AVR device class for AT90CAN64, see AvrDevice_at90canbase.
Definition: at90canbase.h:117
IOReg< HWTimer16 > ocrc_h_reg
output compare C register, high byte
Definition: hwtimer.h:316
AvrFuses * fuses
Definition: avrdevice.h:100
PrescalerMultiplexer premux1
prescaler multiplexer for timer 0
Definition: at90canbase.h:63
PrescalerMultiplexer premux2
prescaler multiplexer for timer 0
Definition: at90canbase.h:64
AddressExtensionRegister * rampz
RAMPZ address extension register.
Definition: avrdevice.h:105
AVR device class for AT90CAN32, see AvrDevice_at90canbase.
Definition: at90canbase.h:110
AVR device class for AT90CAN128, see AvrDevice_at90canbase.
Definition: at90canbase.h:124
HWIrqSystem * irqSystem
Definition: avrdevice.h:104
IOReg< HWAd > admux_reg
Definition: hwad.h:269
Implements a stack with stack register using RAM as stackarea.
Definition: hwstack.h:131
HWSpi * spi
spi unit
Definition: at90canbase.h:74
IOReg< HWUart > ubrrhi_reg
IO register "UBRRxH" - baudrate.
Definition: hwuart.h:136
IOReg< HWEeprom > eedr_reg
Definition: hweeprom.h:101
IOReg< HWTimer8_1C > tccr_reg
control register
Definition: hwtimer.h:388
void registerIrq(int vector, int irqBit, ExternalIRQ *extirq)
Definition: externalirq.cpp:53
IOReg< HWTimer16 > ocra_h_reg
output compare A register, high byte
Definition: hwtimer.h:312
Implement CLKPR register.
Definition: rwmem.h:135
HWPort portf
port F
Definition: at90canbase.h:56
IOSpecialReg gtccr_reg
GTCCR IO register.
Definition: at90canbase.h:58
Pin & GetPin(unsigned char pinNo)
returns a pin reference of pin with pin number
Definition: hwport.cpp:87
Timer unit with 8Bit counter and one output compare unit.
Definition: hwtimer.h:377
IOReg< HWTimer16 > ocra_l_reg
output compare A register, low byte
Definition: hwtimer.h:313
IOReg< HWAcomp > acsr_reg
ACSR IO register.
Definition: hwacomp.h:82
IOReg< HWTimer8 > tcnt_reg
counter register
Definition: hwtimer.h:229
Definition: hwwado.h:38
A register in IO register space unrelated to any peripheral. "GPIORx" in datasheets.
Definition: rwmem.h:113
IOReg< HWTimer16 > tcnt_h_reg
counter register, high byte
Definition: hwtimer.h:310
CLKPRRegister * clkpr_reg
CLKPR IO register.
Definition: at90canbase.h:93
PrescalerMultiplexerExt premux0
prescaler multiplexer for timer 0
Definition: at90canbase.h:62
Handler for external IRQ&#39;s to communicate with IRQ system and mask/flag registers.
Definition: externalirq.h:41
IOReg< HWTimer16 > ocrc_l_reg
output compare C register, low byte
Definition: hwtimer.h:317
Represents a timer interrupt line, Frontend for timer interrupts.
Definition: timerirq.h:42
PrescalerMultiplexerExt premux3
prescaler multiplexer for timer 0
Definition: at90canbase.h:65
void SetFuseConfiguration(int size, unsigned long defvalue)
Configure fuses.
Definition: flashprog.cpp:246
HWUsart * usart0
usart 0 unit
Definition: at90canbase.h:76
IOReg< AddressExtensionRegister > ext_reg
Definition: ioregs.h:45
IOReg< HWUart > ubrr_reg
IO register "UBRRxL" - baudrate.
Definition: hwuart.h:136
HWAd * ad
adc unit
Definition: at90canbase.h:73
IOSpecialReg tifr_reg
the TIFRx register
Definition: timerirq.h:74
IOReg< HWAd > adcsrb_reg
Definition: hwad.h:269
ExternalIRQHandler * extirq01
external interrupt support for INT0, INT1, INT2, INT3, INT4, INT5, INT6, INT7
Definition: at90canbase.h:66
IOReg< HWSpi > spdr_reg
Definition: hwspi.h:121
Implements the I/O hardware necessary to do USART transfers.
Definition: hwuart.h:149
IOSpecialReg * eimsk_reg
EIMSK IO register.
Definition: at90canbase.h:69
IOReg< HWPort > port_reg
Definition: hwport.h:84
IOReg< HWUart > ucsra_reg
Definition: hwuart.h:136
void Reset()
Definition: avrdevice.cpp:390
IOReg< HWPort > pin_reg
Definition: hwport.h:84
IOReg< HWTimer16 > icr_h_reg
input capture register, high byte
Definition: hwtimer.h:318
OSCCALRegister * osccal_reg
OSCCAL IO register.
Definition: at90canbase.h:94
IOReg< HWSpi > spcr_reg
Definition: hwspi.h:121
GPIORegister * gpior1_reg
Definition: at90canbase.h:91
HWPort portb
port B
Definition: at90canbase.h:52
ICaptureSource * inputCapture3
input capture source for timer3
Definition: at90canbase.h:86
TimerIRQRegister * timerIrq3
timer interrupt unit for timer 3
Definition: at90canbase.h:87
TraceValueCoreRegister coreTraceGroup
Definition: avrdevice.h:108
IOReg< HWUart > ucsrb_reg
Definition: hwuart.h:136
IOReg< HWTimer16 > icr_l_reg
input capture register, low byte
Definition: hwtimer.h:319
HWPort porte
port E
Definition: at90canbase.h:55
HWTimer8_1C * timer2
timer 2 unit
Definition: at90canbase.h:84
HWPort portg
port G
Definition: at90canbase.h:57
IOReg< HWAd > adcsra_reg
Definition: hwad.h:269
IOReg< HWEeprom > eearh_reg
Definition: hweeprom.h:101
IOReg< HWTimer16_3C > tccra_reg
control register A
Definition: hwtimer.h:678
IOReg< HWTimer16 > tcnt_l_reg
counter register, low byte
Definition: hwtimer.h:311
IOSpecialReg * eicrb_reg
EICRA IO register.
Definition: at90canbase.h:68
HWPort portc
port C
Definition: at90canbase.h:53
Pin * GetPin(const char *name)
Definition: avrdevice.cpp:76
IOReg< HWTimer16_3C > tccrc_reg
control register C
Definition: hwtimer.h:680
IOReg< HWTimer16 > ocrb_l_reg
output compare B register, low byte
Definition: hwtimer.h:315
Timer unit with 16Bit counter and 3 output compare units.
Definition: hwtimer.h:656
TimerIRQRegister * timerIrq0
timer interrupt unit for timer 0
Definition: at90canbase.h:78
Provices flag and mask register for timer interrupts and connects irq lines to irqsystem.
Definition: timerirq.h:61
ADC type M164: ADC on atmega164/324/644/1284 and at90can32/64/128.
Definition: hwad.h:264
IOReg< HWEeprom > eecr_reg
Definition: hweeprom.h:101
HWEeprom * eeprom
Definition: avrdevice.h:102
Definition: hwspi.h:38
void registerLine(int idx, IRQLine *irq)
Definition: timerirq.cpp:88
#define AVR_REGISTER(name, class)
Definition: avrfactory.h:69
RWMemoryMember ** rw
The whole memory: R0-R31, IO, Internal RAM.
Definition: avrdevice.h:129
TimerIRQRegister * timerIrq2
timer interrupt unit for timer 2
Definition: at90canbase.h:83
HWPort portd
port D
Definition: at90canbase.h:54
oscillator version 4.x, 7bit, one range
Definition: rwmem.h:180
Provides the programming engine for flash self programming.
Definition: flashprog.h:38
IOSpecialReg * eicra_reg
EICRA IO register.
Definition: at90canbase.h:67
void SetBootloaderConfig(unsigned addr, int size, int bPosBOOTSZ, int bPosBOOTRST)
Set bootloader support configuration.
Definition: flashprog.cpp:274
IOReg< HWAd > adch_reg
Definition: hwad.h:269
IOReg< HWTimer16 > ocrb_h_reg
output compare B register, high byte
Definition: hwtimer.h:314
IOReg< HWSpi > spsr_reg
Definition: hwspi.h:121
HWAcomp * acomp
analog compare unit
Definition: at90canbase.h:75
IOReg< HWEeprom > eearl_reg
Definition: hweeprom.h:101
HWTimer8_1C * timer0
timer 0 unit
Definition: at90canbase.h:79
HWAdmux * admux
adc multiplexer unit
Definition: at90canbase.h:71
IOReg< HWAd > adcl_reg
Definition: hwad.h:269
IOReg< HWTimer8 > ocra_reg
output compare A register
Definition: hwtimer.h:230
static NotSimulatedRegister * getRegister(int reg)
Definition: rwmem.cpp:297
HWStack * stack
Definition: avrdevice.h:131
Class, which provides input capture source for 16bit timers.
Definition: icapturesrc.h:34
RWSreg * statusRegister
the memory interface for status
Definition: avrdevice.h:133
IOReg< HWUart > udr_reg
Definition: hwuart.h:136
IOReg< HWTimer16_3C > tccrb_reg
control register B
Definition: hwtimer.h:679
HWARef * aref
adc reference unit
Definition: at90canbase.h:72
IRQLine * getLine(const std::string &name)
Definition: timerirq.cpp:109
IOSpecialReg * eifr_reg
EIFR IO register.
Definition: at90canbase.h:70
HWWado * wado
WDT timer.
Definition: avrdevice.h:134
Definition: hwad.h:204
TimerIRQRegister * timerIrq1
timer interrupt unit for timer 1
Definition: at90canbase.h:81
AvrDevice_at90canbase(unsigned ram_bytes, unsigned flash_bytes, unsigned ee_bytes)
Definition: at90canbase.cpp:73
FlashProgramming * spmRegister
Definition: avrdevice.h:99
HWPort porta
port B
Definition: at90canbase.h:51
ICaptureSource * inputCapture1
input capture source for timer1
Definition: at90canbase.h:80
HWTimer16_3C * timer1
timer 1 unit
Definition: at90canbase.h:82
IOReg< HWPort > ddr_reg
Definition: hwport.h:84
IOReg< HWWado > wdtcr_reg
Definition: hwwado.h:54
IOReg< HWUsart > ucsrc_reg
Definition: hwuart.h:173
IOSpecialReg timsk_reg
the TIMSKx register
Definition: timerirq.h:73
GPIORegister * gpior2_reg
Definition: at90canbase.h:92
HWTimer16_3C * timer3
timer 3 unit
Definition: at90canbase.h:88
Analog comparator peripheral.
Definition: hwacomp.h:42
IOReg< FlashProgramming > spmcr_reg
Definition: flashprog.h:95
Implement OSCCAL register.
Definition: rwmem.h:174
External interrupt (INT0, INT1...) on a single pin, one and 2 bit configuration.
Definition: externalirq.h:110
bool flagELPMInstructions
ELPM instructions are available (only on devices with bigger flash)
Definition: avrdevice.h:120
IOSpecialReg assr_reg
ASSR IO register.
Definition: at90canbase.h:59