49 #define SPI2X 0x01 //only on mega devices speed x 2 96 int fac2x=(spsr&
SPI2X) ? 1 : 2;
98 case 0: clkdiv=1;
break;
99 case SPR0: clkdiv=4;
break;
100 case SPR1: clkdiv=16;
break;
114 <<
"spsr is read only! (0x" << hex << core->PC <<
" = " <<
115 core->Flash->GetSymbolAtAddress(core->PC) <<
")" << endl;
123 core->AddToCycleList(
this);
125 MISO.SetUseAlternateDdr(1);
126 MISO.SetAlternateDdr(0);
127 MOSI.SetUseAlternatePortIfDdrSet(1);
132 MOSI.SetAlternatePort(1);
133 SCK.SetAlternatePort(spcr &
CPOL);
134 SCK.SetUseAlternatePortIfDdrSet(1);
136 assert(SCK.GetPin().outState == ((spcr &
CPOL) ?
Pin::HIGH : Pin::LOW));
138 MISO.SetUseAlternatePortIfDdrSet(1);
139 MOSI.SetUseAlternateDdr(1);
140 MOSI.SetAlternateDdr(0);
141 SCK.SetUseAlternateDdr(1);
142 SCK.SetAlternateDdr(0);
143 SS.SetUseAlternateDdr(1);
144 SS.SetAlternateDdr(0);
153 core->RemoveFromCycleList(
this);
154 MOSI.SetUseAlternatePortIfDdrSet(0);
155 MISO.SetUseAlternatePortIfDdrSet(0);
156 SCK.SetUseAlternatePortIfDdrSet(0);
157 MOSI.SetUseAlternateDdr(0);
158 MISO.SetUseAlternateDdr(0);
159 SCK.SetUseAlternateDdr(0);
160 SS.SetUseAlternateDdr(0);
176 MOSI(mosi), MISO(miso), SCK(sck), SS(ss),
177 irq_vector(ivec), mega_mode(mm),
178 spdr_reg(this,
"SPDR", this, &
HWSpi::GetSPDR, &
HWSpi::SetSPDR),
179 spsr_reg(this,
"SPSR", this, &
HWSpi::GetSPSR, &
HWSpi::SetSPSR),
180 spcr_reg(this,
"SPCR", this, &
HWSpi::GetSPCR, &
HWSpi::SetSPCR)
205 cerr <<
"WARNING: There is HWSPI called to get a irq vector which is not assigned for!?!?!?!?";
268 switch ((
clkcnt/clkdiv)&1) {
324 bool leading =
false;
332 bool sample = leading ^ ((
spcr&
CPHA)!=0);
Basic AVR device, contains the core functionality.
void trxend()
Handle end of transmission if necessary.
void spdr_access()
Called for all SPDR access to clear the WCOL and SPIF flags if needed.
void ClearIrqFlag(unsigned int)
void SetSPCR(unsigned char val)
HWSpi(AvrDevice *core, HWIrqSystem *, PinAtPort mosi, PinAtPort miso, PinAtPort sck, PinAtPort ss, unsigned int irq_vec, bool mega_mode=true)
void txbit(const int bitpos)
Send/receive one bit.
#define CPOL
"When this bit is written to one, SCK is high when idle."
void updatePrescaler()
Takes info from registers and updates clkdiv.
bool finished
finished transmission?
void SetAlternatePort(bool val)
Build a register for TraceValue's.
void SetIrqFlag(Hardware *, unsigned int vector_index)
void SetSPDR(unsigned char val)
void SetSPSR(unsigned char val)
void rxbit(const int bitpos)
void DebugVerifyInterruptVector(unsigned int vector_index, const Hardware *source)
In datasheets RESET vector is index 1 but we use 0! And not a byte address.
#define CPHA
When this bit is written to one, output is setup at leading edge and input is sampled trailing edge...
void ClearIrqFlag(unsigned int vector_index)
#define DORD
"When the DORD bit is written to one, the LSB of the data word is transmitted first."
TraceValue * trace_direct(TraceValueRegister *t, const std::string &name, const bool *val)
Register a directly traced bool value.